Current design and execution ledgers¶
Current code uses unified physical directories, TOML static assembly, typed factories and shared polymorphic tables. Public C11 faces contain only read-only ops and private context. Each instance owns independent state; callers supply request and block storage. SDKs/provider storage remain private and product projects external. Use these design contracts together with current delivery; historical documents establish no current qualification.
For assembly, borrow and recovery responsibilities of five bounded software increments, see mapped storage, AMP, image handoff, RTC and frame boundaries. The complete original exit conditions and hardware status remain unchanged.
Document |
Purpose |
|---|---|
Nine boundaries covering application entry, configuration explanations, instance integration, lifecycle, resource cost, official reuse and execution efficiency |
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63 software items, six integration exits and six physical exits; implementation and actual verification remain separate |
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Target design for reader tasks, one canonical source, MyST/API, bilingual content, gates, versions and offline delivery |
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Preserve DOC-01–40 and add content/diagram tasks; separately record dependencies, exit conditions and implementation/verification |
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Reader list derived from the same ledger without another status authority |
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Clear writing, normative language, facts/qualification, examples, architecture diagrams and independent review |
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Required questions for tutorial/how-to/reference/explanation/status pages |
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Local DOT/SVG main figures and two supplements; the figure index defines the main set, with current/reference/target identity, rendering and review recorded separately |
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Destinations for canonical content, tools and adjacent READMEs; retain original qualification and ledger identities |
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Principles, execution, ownership, performance/storage and support boundaries |
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Eight groups covering paths, configuration, builds and verification; implementation, software execution and physical status are recorded separately |
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Resource/trigger/DMA plans, optional traits, silicon admission, data units and current/pending boundaries; IO-01–42 owns status |
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Exact acquisition protocols for H743 SPI Cache/continuous RX/UART DMA duplex and U575 UART hardware chains/RUN LPTIM; preparation and raw-record validation do not establish physical qualification |
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Reviewed V-cut HSI/PLL384 cold lifecycle, immutable clock domains and peripheral kernel contracts; software evidence and unverified hardware limits |
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Selected V/cache-off private CPU bridge, RAM VTOR, MPU protection and real drain; production-ELF closure and complete software exits remain open |
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One owner, two primes, TIM1-triggered regular ADC DMA, drain and cold recovery; software reference/HIL boundaries |
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Exact TZEN0 USART1 finite GPDMA TX, persistent DMAT, SRAM1 admission and request/wire/IRQ drain |
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Fixed FDCAN1 message RAM, explicit mode, physical TX completion and reference drain; transceiver and hardware boundaries |
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H743/U575 official LL thresholds, RX/TX budgets, IDLE short tails and TC drain; formal configuration and hardware boundaries |
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G474 regular/injected groups, silicon revision admission, sample format, calibration freshness and proven stop; product algorithms remain external |
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F407/GD470 SG/VLAN, frame borrowing, hardware timestamps and global abort; PHY and protocol policy remain external |
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Exact VE/ZG baremetal, external CK/WS, finite normal-mode DMA, whole-block frame borrowing and actual drain; development software evidence is separate from full audio/physical exit conditions |
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Record per-configuration development evidence, source awaiting freeze and final qualification separately; inherit neither old CI nor hardware qualification |
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Existing formatting/comments, tools, automation, evidence and publication |
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Configuration transactions, incremental dependencies, target policy, developer entry and delivery boundaries |
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Original exit conditions, implementation paths and iteration execution evidence |
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Private HAL/LL reuse, typed Construction, work-package exits and qualification boundaries |
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Eight exact parts, official and Zephyr sources, finite peripheral boundaries and cross-family platform feedback |
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Strict resource contracts for SoC/Board/devices/components/external projects |
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Deadlines, IRQ policy, tasks/queues, low power and extension boundaries |
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New RTOS capability contracts, actual execution and prohibition on automatic support expansion |
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Real official Linux/M4 kernels, independent typed policy, bootstrap, static objects and exact support scope |
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Explicit FreeRTOS selector, fixed clock/compare alarms, quantized phase, retained failure and physical boundaries |
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TZEN0 independent RTC domain, explicit WUT owner, RUN barrier and retained failed-drain ownership; general LPBAM and physical exits remain open |
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Exact LPDMA1ch0, two finite byte blocks, AlarmA14 and WUT escape; settlement follows all RTC/DMA/IRQ/gate/clock withdrawal, while full LPBAM and physical exits remain open |
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Exact SRAM4→LPTIM1 CCR1/RCR/ARR, REQ13/BREQ1/DREQ0 and explicit start/stop; compound release by the same owner, no pin route, and original IO-32/SOC-35 exits remain open |
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Three mailboxes, shared filter domain, controller-local abort/recovery and Board electrical handoff |
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PIO packet/endpoint ownership, independent 48 MHz owner, control epochs and complete stop |
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Caller descriptors/RX loans, RMII and optional DP83848; external protocols and PHY/Board policy |
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Capture events and complementary PWM/deadtime/break; shared resources and actual safety boundaries |
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Kernel-invoked scalar GPIO and copied UART TX; trusted principal/copy/session authority; U575 synchronous reference transport is covered by the dual-world contract |
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One active finite SDR/DAA/CCC request and copied IBI/hot-join events; H563 is a compile-only reference with no physical provider |
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Actual ARM builds per authored fixture, resource budgets, link retention and immutable inputs |
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Independent provider/IRQ/DMA ownership; configuration availability and silicon implementation recorded separately |
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Exact part, MB1367, six UARTs, package GPIO, finite SPI, TIM3/4 CH1 PWM, IWDG and PA0/PA1 EXTI |
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Four fixed HSI/Cache profiles and cold Cache ownership; separate V/HSI64/baremetal references add finite SPI4 DMA, continuous USART3 RX/IRQ TX and an explicitly selected finite TX-DMA/continuous RX duplex mode |
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Independent Secure/NS Runtime, cold-attribution seal, fixed NS world and synchronous GPIO; no expanded RTOS/factory/async/HIL promise |
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Separate implementation scope, original exits, software mechanisms and physical acceptance |
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Caller-exclusive GPIO, finite timing and continued cleanup after failures |
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Finite/continuous receive, duplex DMA, flow control and actual TC/DE timing |
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Actual mechanisms, evidence and software/physical status per item |
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Nine-core software, atomics, cache/MPU/SAU and security boundaries |
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Separate implementation files, evidence entries and software/physical status |
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Factory, TOML, TDD, multiple instances and IRQ/DMA/block implementation |
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Stateless narrow observation, preserved interrupt masks, external safe outputs and physical boundaries |
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203 bounded properties, actual production compilation, one test execution and provenance validation |
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Separate implementation, software execution, boards and external blockers; Codex owns all maintenance |
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Current directories, public factories/polymorphic interfaces and dependency direction |
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Distinguish development execution, clean software candidates and pending boards |
Ledgers retain B0–B6 and original exit conditions, adding implementation_paths/evidence_paths, software_status and hardware_status. Implemented means mechanisms exist, not every exit passed. Development cannot replace clean-source SDKs, formal offline dual builds or candidate sealing. Formal NG028/030 executions update freshly generated evidence. Hardware is disconnected and all applicable physical items are not_executed. Glob denotes explicit directory families of one mechanism, not recursive discovery or default builds; X-Gen-Lab/nexus-examples paths belong to a separate repository.
CPU software covers M0/M0+/M3/M4/M7/M23/M33/M55/M85, selecting atomic backends, ABI, optional FPU/MVE/cache/MPU/SAU and baremetal/FreeRTOS ports through explicit CPU/IRQ facts. External CPU runtime generates no SoC/Board/factory. ThreadX maintains a separate explicit Native/M4 subset and inherits no nine-core FreeRTOS scope. See nine-core support for configurations and outstanding conditions. This does not expand whole-platform chip/board scope.
First-release references are Qiming STM32F407ZGT6, Sky STM32F407VET6 and Liangshan GD32F470ZGT6, with baremetal/FreeRTOS, explicit ThreadX and Native models. New F103RBT6/GD32F303RCT6 references and G474/H743/U575 increments follow each contract’s exact configuration, complete-image and SDK exits; public types do not imply whole-family or all-peripheral support. F103/GD303 add finite UART channel-DMA, IRQ I2C, physical Flash, single-shot ADC and fixed PWM. GD303 also maintains EXTI and a hardware-cascaded timebase. G474 adds bulb ADC shots/finite TIM6 DMA, I2C1 and ECC Flash beside GPIO/UART/SPI/PWM/IWDG/EXTI. H743 fixed HSI/Cache supports finite TX DMA or RX blocks with rearm gaps and explicitly initialized D2 SRAM1. Separate V/HSI64/baremetal references add finite SPI4 DMA and continuous double-buffered USART3 RX with Cache off/on. rx-dma-continuous retains independent IRQ TX; only the separately selected dma-duplex-continuous adds finite TX DMA. The new duplex mode admits only AXI SRAM, with at least three equal RX blocks; it does not imply FreeRTOS, PLL384 or D2 SRAM support. Seven other finite peripheral classes have software fixtures. U575 TZEN0 adds SPI/I2C/ADC/PWM/EXTI/Flash with external supply and security-state admission. Its independent no-OS TZEN1 GPIO reference copies up to eight commands into a Secure slot for caller-driven progress; it retains no NS pointer and does not provide a generic dual-world factory, NS RTOS or asynchronous borrow. The public Flash contract owns ECC program_flags, fresh-erase provenance and per-pulse completion. Current implementation and final integrated qualification are recorded separately without inherited historical counts. The bounded SOC-33 software increment is described by the boundary page above; its complete exits remain open. SOC-34 running frequency changes remain unimplemented. SOC-35 adds the bounded U575 retained-time reference: an independent RTC domain, explicit WUT/Stop2 owner and retained failed-drain ownership. Old default Core TIM2 deadlines become invalid after stop. A separately selected finite SRAM4/LPDMA copy uses the same owner; general peripheral LPBAM, physical copy/retention/precision/power/wake acceptance and the complete exit remain open. SOC-36 remains partial, and SOC-37–55 physical acceptance not_executed. Unobserved PCB facts for the three Boards remain unknown; software fixtures do not become actual Board routes. The ten-person capacity model remains TL1, Core/I/O/OS2, BSP2, common applications/communications2, QA/HIL2 and build/release1. Codex owns all maintenance without requiring named accounts. Remote branch protection must be independently observed through GitHub rather than inferred from local role files.
The separately selected single-tuple LPTIM1 LPBAM updates dedicated LPTIM1 from one SRAM4 CCR1/RCR=0/ARR tuple through LPDMA1 channel0. It uses the same concrete Stop2 owner; public start/stop retain restoration responsibility after partial startup failure. This software slice establishes no general LPBAM, pin route or physical acceptance, and leaves the original IO-32/SOC-35 exit conditions unchanged.
Behavior changes follow RED → GREEN → REFACTOR. Host GoogleTest/GoogleMock tests execute real providers, factories and owners; configuration tools use Python unittest. Commit hooks and CI run the same gate; MCU targets link no test frameworks. Build-time resources, actual register models, ARM ELF budgets and physical HIL establish separate evidence; actual linked images measure method-table overhead.