Maintained design contracts¶
These maintained contracts and active plans describe mechanisms, invariants and exit conditions. Historical documents are excluded from the current site and search.
- Current design and execution ledgers
- Finite ADC sequences with explicit integer frames
- CPU, atomics and runtime assembly contracts
- Build system maintenance contract
- CAN FD with fixed physical RAM and explicit request ownership
- Classic CAN mechanisms and integration boundaries
- Explicit clock leases and shallow sleep
- Developer experience and provider iteration
- Nexus complete documentation-system improvement checklist
- Nexus documentation content and diagram standards
- Nexus documentation-system architecture and delivery plan
- Nexus documentation page templates
- Next-generation platform engineering handbook
- Raw Ethernet MAC, MDIO and DP83848
- Ethernet frame loans and the MAC hardware clock
- Finite I2S2 slave TX on STM32F407
- Fault observation and retained responsibility
- H743 Flash maintenance from a private RAM execution pod
- H743 V-only high-clock profile
- Explicit I2C bus recovery
- Bounded I3C controller core
- Integration, resource assembly and source-SDK contract
- I/O evolution: static resources and explicit data contracts
- Mapped storage, AMP, image handoff, RTC and frame boundaries
- Bounded I/O lifecycle property matrix
- I/O observations, capacity and retained recovery
- Mainstream MCU adaptation and feedback
- Multiple controller ownership
- Independent finite UART and SPI DMA controllers
- Nexus next-generation platform: design from first principles
- Official drivers and provider iteration
- OS backend integration
- OS execution and lifecycle contract
- Selected provider assembly gate
- Finite PWM and ADC windows with one hardware owner
- Exact selected-mode HIL preparation
- SoC execution budgets
- SoC refinement and physical acceptance
- Source versions, factory generations and dependency maintenance
- Stack observations and owner lifecycle endurance
- STM32G474RET6 / MB1367 selected peripheral platform
- ThreadX configuration and integration
- Reviewed shallow tickless timebase
- Optional timer capture and complementary PWM
- U575 single-tuple LPTIM1 LPBAM across Stop2
- U575 MPU-v2 scalar GPIO WRITE authority
- U575 retained elapsed-time domain
- U575 finite SRAM4 copy across Stop2
- U575 dual-world GPIO reference contract
- Finite USART1 GPDMA TX on STM32U575
- UART receive DMA, duplex DMA and electrical adaptation
- Bounded UART hardware FIFO bytes
- USB FS device packet ownership and integration boundaries
- Kernel-invoked user I/O admission