Document source: 58297516d707; code reference: 58297516d707. 中文. Source language: zh_CN; requested: en; actual: en; translation: reviewed.

Source documentation does not establish software or physical hardware qualification. See the support and qualification records for their exact scope.

Exact support scope

The derived capability matrix automatically checks SoC/route modes, reference-Board bindings and production sources selected by the actual resolver/emitter. Narrative tables describe runtime contracts; derived tables describe exact identities and bounded source consistency. Neither inherits old-HEAD qualification nor replaces physical execution.

Chips, Boards and systems

Target	Software implementation	Unfinished physical facts
STM32F407ZGT6 / Qiming Xinxin V3.1	Cortex-M4F; 1 MiB Flash; main SRAM 128 KiB, CCM 64 KiB; declared clock/profile and reviewed routes	Actual PCB revision, crystal, power, continuity, waveforms and loads
STM32F407VET6 / Sky Star Youth Edition	Cortex-M4F; 512 KiB Flash; main SRAM 128 KiB, CCM 64 KiB; independent Board resources	Corresponding actual PCB/electrical/HIL acceptance
GD32F470ZGT6 / Liangshan Pi	Cortex-M4F; 1 MiB Flash; main SRAM 192 KiB, ADDSRAM 256 KiB, TCM 64 KiB; declared 25 MHz input, 200 MHz profile; optional independent 48 MHz USB owner	PCB/crystal/electrical facts unobserved; default linker uses main SRAM only; actual USB clock/PHY unmeasured
STM32G474RET6 / MB1367 source-reference configuration	Cortex-M4F; 512 KiB Flash; contiguous 128 KiB CPU SRAM alias; HSE24/170 MHz, independent TIM2; GPIOA PA5, LPUART1 PA2/PA3 IRQ bytes; PA0/PA1 selected-EXTI software fixture; generated factory and baremetal/FreeRTOS ELF	Actual PCB/crystal/solder bridges/EXTI wiring unobserved; no DMA authorization; software reports separate from actual PCB/electrical acceptance
STM32H743ZIT6 / NUCLEO-H743ZI2 source-reference configuration	Cortex-M7F; 2 MiB Flash; default AXI SRAM 512 KiB; pre-RAM LDO, fixed HSI32/HSI64 × Cache off/on, TIM2; PB0 GPIO, USART3 PD8/PD9 IRQ bytes or bounded TX DMA; baremetal/FreeRTOS static assembly	PCB/power/silicon revision/solder bridges/Cache coherence unobserved; RX remains IRQ bytes; no RX DMA, alternate RAM placement or running-state handover; final software qualification recorded separately
STM32U575ZIT6Q / NUCLEO-U575ZI-Q single-state reference configuration	Cortex-M33F; 2 MiB Flash; default SRAM1 192 KiB; externally preconfirmed TZEN=0/SWAP_BANK=0; MSIS4 MHz, TIM2; PC7 GPIO, USART1 PA9/PA10 IRQ bytes; baremetal/FreeRTOS static assembly	PCB/SMPS/silicon revision/option bytes unobserved; Cache disabled; this Platform exposes no DMA, split-domain factory or alternate RAM placement; final software qualification recorded separately
Independent STM32U575 TZEN=1 split-domain reference	Externally preconfigured option bytes; two Runtime images, cold SAU/MPU/SRAM-attribution owner, actual CMSE SG; one unprivileged NonSecure Thread accesses restricted PC7 GPIO through synchronously copied messages	No physical-isolation acceptance; no OS, generic split-domain factory, NS task identity, asynchronous borrow/cross-domain DMA or product-image authentication; does not change default TZEN=0 assembly above
Native	Linux/POSIX behavior model with actual threads/persistent-file fault models	No MCU or electrical qualification

Baremetal/pinned FreeRTOS are explicitly selected thin adapters. Startup establishes platform clocks/interfaces only, without schedulers, product tasks or workflows. FreeRTOS POSIX host execution verifies software lifecycle, not MCU IRQ ceilings, FPU context or physical stack high-water.

H743 uses official Cortex-M7 startup/bounded LDO entry and forbids RAM writes before ACTVOSRDY, establishing selected clocks/Cache from trusted HSI64/Cache-off cold state. Disabled Cache bits do not prove foreign dirty data clean; trusted reset/prior successful owned clean-disable is required. Default U575 Platform uses official Cortex-M33 startup/TZEN=0 single-address state. Independent TZEN=1 has separate entry/security owner. Reading option registers after startup cannot legalize incompatible startup. Neither changes option bytes or automatically takes over bootloaders, DMA or existing clock/IRQ owners. Original CMSIS Device H7/U5 bytes/licenses/versions are source-locked. Entries: H743, U575.

ThreadX is an additional explicit backend pinned to official Eclipse ThreadX 6.5.2.202603. Configuration maintains Cortex-M4 GNU on three F407/F470 Boards and Native Linux GNU. Independent CPU runtime maintains M4 integer/M4F hard-softfp with BASEPRI/PRIMASK policies; other Cortex-M ThreadX ports reject. Production graphs, actual Linux task/queue/join and three-board ARM links are verified separately. Linux pthread stacks/internal host allocations are not MCU cost. ThreadX implements none of this project’s FreeRTOS MPU/split-security/tickless modes. See ThreadX. Platform start enters no kernel; products enter explicitly. Running schedulers cannot lose clock/Tick through ordinary I/O shutdown.

CPU software additionally supports M0/M0+/M3/M4/M7/M23/M33/M55/M85. One strict fact parser selects Core/Arch/atomics/baremetal-FreeRTOS runtime. M0/M0+ RMW uses bounded saved-PRIMASK. Optional cache/MPU/SAU execute real CPU algorithms; FPU/MVE/security choose exact kernel ports/ABI. CPU-only runtime generates no SoC/Board/factory. H743/U575 slices separately own assembly/acceptance. Compilation, register models and actual FP/MVE/cache/MPU/security-world acceptance are recorded separately. cache.h range maintenance and M7-only cold control are separate; CMSE permission observation alone provides no user-memory pin/copy/transport. Restricted-MPU-task/split Secure-NonSecure runtime have independent software implementations with separately verified narrow delay/tick SVC, Secure-context leases and caller static storage. Default remains privileged single-world; MPU+split rejects; no physical HIL added. See Cortex-M and Arch contracts.

Launch modes

The full peripheral table below describes F407/F470 launch implementations. G474 additionally maintains selected EXTI; H743 fixed Cache/bounded UART TX DMA; default U575 GPIO/IRQ UART with separately maintained synchronous split-domain GPIO. Chip names/generic interfaces imply no additional peripherals, DMA, ThreadX or low-power modes.

Interface	Implemented modes and limits
GPIO	Authorized mask, atomic set/reset, snapshot read and single-writer toggle
UART	8N1 IRQ TX or bounded TX DMA; caller-owned requests, actual TC; IRQ RX blocks/IDLE, bounded/continuous RX DMA and duplex DMA; explicit RTS/CTS/external static RS485 adapter; STM minimum baud 1282, GD minimum 1526, maximum 1 Mbaud
SPI	8-bit MSB-first; short polling ≤256 bytes/transaction; bounded DMA ≤65535 bytes; incrementing bidirectional spans or caller one-byte fixed dummy/discard; one wire-active operation, complete CS interval, separate CS endpoints
I2C	100 kHz; ≤8 messages, read/write 1–256 bytes each; polling/IRQ/DMA messages; 1/2/final-three-byte ACK, repeated START/NACK/arbitration/STOP; recovery checks BUSY/selected SCL-SDA levels; separate bounded GPIO bus-clear tool
Flash	STM exact 16/64/128 KiB sectors and x32 program (4-byte alignment/length, declared 2.7–3.6 V); GD official independent 4 KiB page erase/halfword program; complete physical space with external restricted regions
Watchdog	Independent enable/feed/reset cause; irreversible enable, retained responsibility after late failure; GD IRC32K physical timeout bounds not guaranteed
EXTI	Selected lines, shared vectors, caller-sized event queues, visible loss/coalescing; no debounce policy
PWM	Fixed timer/channel/base, CCR shadow, 0/100%, safe inactive; public stop permits restart, platform teardown releases owner
ADC	Reviewed channels, single-shot/low-rate scan, bounded/continuous double-buffer timer-triggered DMA blocks; explicit sample time/reference; complete scans only; optional external sequences/software observation timestamps
Classic CAN	11/29-bit DATA/RTR, 0–8 bytes, three real mailboxes/shared filter domain, explicit abort/bus-off recovery; no CAN FD/automatic retransmission
USB FS device	Internal-PHY PIO, EP0 control IN/OUT64, EP1–3 bulk8/16/32/64, packet loans, SETUP epochs, reset/stop drain, independent 48 MHz owner; no Host/HS/DMA/ISO/class stack

USB configuration/factory actually ARM-links on software-Board fixtures for both STM packages/GD470. Default reference Boards expose no automatic USB connector/VBUS electrical facts. vbus_sensing=true rejects absent reviewed electrical facts. PA11/PA12 AF10 silicon routes prove no actual jumpers/power/VBUS/ESD; CAN1/USART1-flow-control conflicts must reject. See USB packet contract.

The following slices have independent production mechanisms/development evidence. Final configuration/SDK/full-image integration are accepted separately. One passed model cannot mean whole-platform/reference-PCB acceptance.

Optional mechanism	Exact scope and current boundary
Raw Ethernet / MDIO / DP83848	Native/ST/GD normal chained descriptors, RMII, 14–1514-byte untagged Ethernet II, caller-owned RX loans; ETH/MDIO faces share one MAC context; ST-ZG/GD-ZG software fixtures have factory/baremetal-FreeRTOS ELFs; no protocol stack/PTP/checksum offload/VLAN/jumbo
Input capture	STM TIM4 CH1 / GD TIMER3 CH0, PB6 AF2, 16-bit modulo counts, caller event rings; software observation time is not edge aperture; assembly integration separately accepted
Complementary PWM / break	STM TIM1 / GD TIMER0, PA8/PB13/PB12 AF1; immutable exact deadtime/BKIN, no automatic restart; no power-stage safety qualification
User I/O broker	Privileged-kernel scalar GPIO read/set-reset with actual principal/pin/copy/unpin narrow ports; independent OS-free U575 synchronous CMSE gateway; no generic SVC/multitask-userspace transport/asynchronous user DMA

Reference Boards declare no default Ethernet PHY/REFCLK/reset wiring. Qiming-ZG optional RMII provenance needs PG11/13/14, unauthorized on VE100. Sky Star/Liangshan Pi lack reviewed PHY routes. External projects own protocols/cables/PHY power-reset/product MAC/recovery. See Ethernet, advanced timers, user I/O broker and G474.

G474 maintains actual generated-factory host contracts, independent system/provider regressions and empty/GPIO-UART/selected-EXTI baremetal-FreeRTOS ARM fixtures. Gates check budgets/table retention/unselected-driver trimming/vector bytes. Reviewed Board documents/pinned official CMSIS prove no actual MCU/X3 crystal/VCP-LD2 bridges. Initial SoC execution retains historical code revision; extensions independently bind later source/evidence. Offline reproduction/candidate sealing have separate exits and inherit no old F407/F470 qualification.

H743 bounded TX DMA maintains only USART3, DMA1 Stream0, DMAMUX1 channel0/request46 and AXI SRAM reachability. Cache on requires caller ownership of complete 32-byte lines and clean before DMA. Neither incomplete preparation nor drain releases borrows. Cache lifecycle is fixed at platform start/stop; all providers drain before timebase withdrawal/cache clean-disable. No RX DMA, other DMA engines, optional RAM layout or live scaling. Independent U575 split partitions/fixed principal/synchronous-borrow premises are in TrustZone.

Ethernet fixtures retain exact TX/RX descriptors/RX buffers and admit only STM main SRAM128 KiB/GD main SRAM192 KiB. Development budget/retention on four ZG ARM graphs authorize no GD ADDSRAM/TCM, STM CCM, VE100 PG routes or product PHY. Independent cold review/clean-source SDK/physical qualification remain separate. Default references select no ETH/MDIO.

Exact bounded-DMA launch routes follow; the resolver rejects other controller/channel combinations.

Mode	STM32F407	GD32F470
UART TX DMA	USART1; DMA2 stream7 channel4	USART0; DMA1 channel7 selector4
UART RX DMA / duplex DMA	USART1; RX DMA2 stream2 channel4; TX as above	USART0; RX DMA1 channel2 selector4; TX as above
SPI full-duplex DMA	SPI1; DMA2 RXstream0/TXstream3 channel3	SPI4; DMA1 RXchannel3/TXchannel4 selector2
I2C message DMA	I2C1; DMA1 RXstream0/TXstream6 channel1	I2C0; DMA0 RXchannel0/TXchannel6 selector1
ADC bounded/continuous trigger blocks	ADC1; TIM3 TRGO; DMA2 stream4 channel0	ADC0; TIMER2 TRGO; DMA1 channel0 selector0

Reviewed software-Board configurations support STM32F407 I2C1/I2C2 and GD32F470 I2C0/I2C1 IRQ/DMA assembly/typed factories. Dual-controller fixtures have independent-instance isolation/real-SDK link evidence. Reference Boards expose declared bindings only; other silicon routes/actual wiring require separate review. See multicontroller ownership.

SPI DMA requires nonempty/nonoverlapping actual TX/RX spans; fixed-address directions access caller one-byte storage only. No scratch/implicit copy pool is allocated. Providers recheck actual memory domains/permissions; STM CCM/GD TCM cannot be DMA buffers. DMA TC is a memory fact; UART TC/SPI idle are line facts. Both drain proofs precede SETTLED. Cancellation/timeout/EN-disable refusal retain borrows in QUARANTINED.

UART irq-blocks keeps independent IRQ RX. rx-dma-idle uses bounded DMA/IDLE, rx-dma-continuous hardware double buffers; explicit dma-duplex/dma-duplex-continuous also exist. Caller blocks remain immutable after consumer acquire until matching-epoch release. Continuous modes reserve two hardware targets/replacement blocks. Replacement-address readback, bank/new-error checks precede old-block publication. No replacement means stop, never overwrite consumer loans. RX-only uses a separate read-only table without TX-DMA methods or corresponding linked code; the shared receive-state layout still contains TX-DMA base fields, so zero cold-field overhead is not claimed. RTS/CTS does not replace capacity/drain. External RS485 supplies DE pin/polarity/setup-hold; actual UART TC precedes hold/DE withdrawal. See UART DMA/RS485.

ADC trigger-dma uses ordinary bounded DMA: stop trigger/conversion/memory writes per block before publishing complete blocks. Callers explicitly service stabilization/GD calibration before next trigger. No free loan means pause without overwriting/invented exact missed samples. Inter-block gaps are expected. trigger-dma-continuous explicitly selects hardware double buffers/preposted blocks, publishing after successful replacement; at least three caller slots are needed. Frequency must satisfy exact timer division/full scan time. GD continuous selects SDK sample-time codes; bounded mode retains 15-cycle samples. Optional timestamps are software publication observations, not sampling apertures. One latched TC/CT cannot count unobserved multiple rounds. Stop with outstanding loans returns BUSY.

I2C IRQ/DMA share a V1 register algorithm checked against both SDK layouts/bits; MCU hot paths access registers directly. DMA TC is not wire completion. Final byte/BTF/STOP-MSL/DMA-EN/IRQ publishers drain before SETTLED. Separate bus-clear requires quiescent peripherals, exclusive open-drain GPIO and bounded waits; at most nine completed pulses. STOP/release failure retains leases for cleanup retries. No automatic pin switching occurs on unreviewed Boards. See I2C recovery.

These are SoC implementation capabilities. Default reference bindings, software-fixture routes and field measurements are independent. STM defaults declare no qualifiable SPI CS; resource matrices measure only empty/GPIO/UART, so fixture SPI does not qualify reference-board SPI. Default GD SPI4 PF6/7/8/9 has public provenance; external NOR exact part remains unknown.

Explicit boundaries

Continuous modes promise no losslessness under arbitrary IRQ latency/consumer speed. I2C reads beyond 256 bytes, dynamic clocks, deep sleep/STOP, secure boot/update and unmaintained modes are unavailable. FreeRTOS lowpower_port="timebase" uses shallow Sleep only on fixed F407/GD470 profiles, requiring SysTick/tickless/single-privileged/no-MPU. Default custom adds no sleep mechanism; CPU-only runtime without SoC timebase rejects the choice. Actual phase/clock continuity/wake latency/power are physically unexecuted; see shallow sleep. Unsupported configurations reject explicitly rather than claim support through successful stubs.

Deadlines cannot cancel Flash pulses; uncleared BUSY retains responsibility. Products own Flash stalls/voltage/watchdog windows/power cuts/authentication/layout/persistent-format migration. Generic storage CRC/commit is not a secure-update protocol.

GD32 Flash relock-readback failure retains static providers/rejects further operations and requires controlled reset; ordinary stop cannot recover it. tests/google/gd32_flash_fault_test.cpp checks postfault read/write/controller-reacquisition refusal, without physical qualification. See security review for lifecycle/scan diagnostics.

Hardware is disconnected. Clock/reset/GPIO-safe-output/UART-TC-abort-RX/SPI-I2C-electrical/Flash-power-cut/watchdog-reset/EXTI-waveform/PWM/ADC-precision execution is absent for every MCU target. Current support cannot replace physical HIL or product-release promotion.