Current design and execution ledgers¶
Current code uses unified physical directories, TOML static assembly, typed factories and shared polymorphic tables. Public C11 faces contain only read-only ops and private context. Each instance owns independent state; callers supply request and block storage. SDKs/provider storage remain private and product projects external. Use these design contracts together with current delivery; historical documents establish no current qualification.
Document |
Purpose |
|---|---|
Target design for reader tasks, one canonical source, MyST/API, bilingual content, gates, versions and offline delivery |
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Preserve DOC-01–40 and add content/diagram tasks; separately record dependencies, exit conditions and implementation/verification |
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Reader list derived from the same ledger without another status authority |
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Clear writing, normative language, facts/qualification, examples, architecture diagrams and independent review |
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Required questions for tutorial/how-to/reference/explanation/status pages |
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17 local SVG/DOT pairs: 15 required diagram categories and 2 supplements; catalogue owns identity and scope |
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Destinations for canonical content, tools and adjacent READMEs; retain original qualification and ledger identities |
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Principles, execution, ownership, performance/storage and support boundaries |
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Existing formatting/comments, tools, automation, evidence and publication |
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Configuration transactions, incremental dependencies, target policy, developer entry and delivery boundaries |
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Original exit conditions, implementation paths and iteration execution evidence |
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Strict resource contracts for SoC/Board/devices/components/external projects |
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Deadlines, IRQ policy, tasks/queues, low power and extension boundaries |
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New RTOS capability contracts, actual execution and prohibition on automatic support expansion |
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Real official Linux/M4 kernels, independent typed policy, bootstrap, static objects and exact support scope |
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Explicit FreeRTOS selector, fixed clock/compare alarms, quantized phase, retained failure and physical boundaries |
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Three mailboxes, shared filter domain, controller-local abort/recovery and Board electrical handoff |
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PIO packet/endpoint ownership, independent 48 MHz owner, control epochs and complete stop |
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Caller descriptors/RX loans, RMII and optional DP83848; external protocols and PHY/Board policy |
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Capture events and complementary PWM/deadtime/break; shared resources and actual safety boundaries |
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Kernel-invoked scalar GPIO and trusted principal/pin/copy; see dual-world contract for separate U575 synchronous reference transport |
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Actual ARM builds per authored fixture, resource budgets, link retention and immutable inputs |
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Independent provider/IRQ/DMA ownership; configuration availability and silicon implementation recorded separately |
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Exact part, MB1367 provenance, clock/startup/time/GPIO/LPUART and PA0/PA1 EXTI software fixtures |
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Four fixed HSI/cache configurations, cold-cache ownership and USART3 DMA TX; RX remains IRQ bytes |
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Independent Secure/NS Runtime, cold-attribution seal, fixed NS world and synchronous GPIO; no expanded RTOS/factory/async/HIL promise |
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Separate implementation scope, original exits, software mechanisms and physical acceptance |
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Caller-exclusive GPIO, finite timing and continued cleanup after failures |
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Finite/continuous receive, duplex DMA, flow control and actual TC/DE timing |
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Actual mechanisms, evidence and software/physical status per item |
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Nine-core software, atomics, cache/MPU/SAU and security boundaries |
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Separate implementation files, evidence entries and software/physical status |
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Factory, TOML, TDD, multiple instances and IRQ/DMA/block implementation |
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Stateless narrow observation, preserved interrupt masks, external safe outputs and physical boundaries |
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203 bounded properties, actual production compilation, one test execution and provenance validation |
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Separate implementation, software execution, boards and external blockers; Codex owns all maintenance |
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Current directories, public factories/polymorphic interfaces and dependency direction |
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Distinguish development execution, clean software candidates and pending boards |
Ledgers retain B0–B6 and original exit conditions, adding implementation_paths/evidence_paths, software_status and hardware_status. Implemented means mechanisms exist, not every exit passed. Development cannot replace clean-source SDKs, formal offline dual builds or candidate sealing. Formal NG028/030 executions update freshly generated evidence. Hardware is disconnected and all applicable physical items are not_executed. Glob denotes explicit directory families of one mechanism, not recursive discovery or default builds; X-Gen-Lab/nexus-examples paths belong to a separate repository.
CPU software covers M0/M0+/M3/M4/M7/M23/M33/M55/M85, selecting atomic backends, ABI, optional FPU/MVE/cache/MPU/SAU and baremetal/FreeRTOS ports through explicit CPU/IRQ facts. External CPU runtime generates no SoC/Board/factory. ThreadX maintains a separate explicit Native/M4 subset and inherits no nine-core FreeRTOS scope. See nine-core support for configurations and outstanding conditions. This does not expand whole-platform chip/board scope.
Launch boards are Qiming STM32F407ZGT6, SkyStar STM32F407VET6 and Liangshan GD32F470ZGT6, with baremetal/FreeRTOS, explicit ThreadX and Native models. New modes and G474/H743/U575 slices use their documented configuration, complete-image and SDK exits; public types do not imply whole-chip integration. G474 adds PA0/PA1 EXTI. H743 supports four HSI 32/64 MHz × Cache off/on startup combinations and finite DMA TX, without runtime reclocking or DMA RX. U575 TZEN0 and independent TZEN1 OS-free synchronous dual-world references remain separate; the latter is not generic dual-world factory, NS RTOS or asynchronous borrowing. SOC-33–35 remain unimplemented; SOC-36 remains partial; SOC-37–55 physical acceptance remains not_executed. Unreviewed physical PCB facts for all three Boards remain unknown; software fixtures are not physical routes. Roles follow the ten-person configuration: TL1, Core/I/O/OS2, BSP2, common applications/communications2, QA/HIL2, build/release1. Codex owns maintenance without named individuals. Remote branch protection needs independent GitHub verification and cannot be inferred from local role files.
Behavior changes follow RED → GREEN → REFACTOR. Host GoogleTest/GoogleMock tests execute real providers, factories and owners; configuration tools use Python unittest. Commit hooks and CI run the same gate; MCU targets link no test frameworks. Build-time resources, actual register models, ARM ELF budgets and physical HIL establish separate evidence; actual linked images measure method-table overhead.