Current platform delivery

The default implementation is Core / Arch / SoC / Board / static factory / polymorphic I/O / optional OS / optional components. One TOML is strictly validated and resolved through immutable IR to generate exact instances. The factory returns stable read-only interface objects with shared read-only operation tables; independent state remains inside each provider. Getting an interface does not start hardware. External projects own applications, product tasks, private PCBs, Flash partitions, recovery and security policy.

Further documentation organization is described in architecture and delivery planning. The documentation tools, prose and figure atlas are implemented; documentation acceptance and firmware qualification are recorded separately. The current entry point is documentation.

Reading entry

Description

Current architecture

Physical directories, dependency direction, execution and resource responsibility

Cortex-M software support

Nine-core ABI/features, Core/Arch/OS runtime and configuration examples

OS delivery

Configuration, explicit storage, external multitasking examples and OS HIL scope

Arch contracts

Context and ownership for atomics, masks, cache/MPU/SAU

Support scope

F407/F470 launch modes, G474/H743/U575 reference vertical slices and exact unknowns

Derived capability matrix

Consistency of facts/routes, reference Boards, software fixtures and production definitions

Software evidence

Actual execution versus pending clean-source sealing

SoC baseline execution record

Exact source, execution results and unexecuted physical boundaries of the sealed baseline

SoC extension execution record

G474 EXTI, H743 Cache/DMA, U575 split-domain reference and subsequent acceptance status

SoC extension results index

Historical SoC fixed source, full CI, offline candidates and archive digests

Build-system contracts

Single configuration authority, CMake target graph, execution and tool boundaries

Build-system execution record

Full software gates, exact candidates and failed attempts for cc6a065c

Build-system results index

Byte identities of source and actual CI, SDK and candidate archives

48-item build implementation ledger

Original exit conditions, implementation and exact software evidence

Migration guide

Migration of old APIs, configuration, objects and external applications

Security and lifecycle review

Scan scope, test-fixture fixes and borrow/recovery restrictions

Next iterations

Physical acceptance, measurement-driven extensions and team workflow

33-item implementation ledger

Implementation paths, evidence entries, software and physical exit status for each item

Factory and TDD iteration ledger

Concrete P0–P5 implementation and conditional acceptance for this iteration

The CPU software layer covers M0/M0+/M3/M4/M7/M23/M33/M55/M85. External projects can use nexus_add_runtime or the installed Runtime component with one strict CPU-runtime TOML/facts package, reusing Core/Arch/I/O faces and the selected baremetal/FreeRTOS adapter. Runtime assembly generates no SoC, Board, startup or factory; external projects still own hardware, product tasks and security policy. The three F407/F470 Boards maintain launch modes; G474/H743/U575 add exact GPIO/IRQ-UART/timebase reference assemblies. G474 additionally has selected EXTI, H743 fixed Cache configuration and limited TX DMA, and U575 an independent OS-free synchronous split-domain reference. These vertical slices do not represent all peripherals or complete security-domain integration; all physical HIL remains unexecuted.

The historical SoC-extension baseline at fixed source 98270512 completed all Native contracts, tool and configuration tests, 121 ARM images, 104 CPU-runtime variants, independent SDK consumption and full GitHub CI. Eight public H743/U575 reference configurations each completed two independent network-disabled builds with byte-identical ELF/BIN and were sealed as unsigned software candidates. Exact scope and raw evidence are in the results index. Later documentation commits only record that source and inherit no new code-execution qualification. Hardware is not connected; all physical HIL is not_executed. Runtime handover, DVFS and continuous deep-STOP timing remain unimplemented; the 55 original exit conditions are unchanged.

This build-system delivery is bound to cc6a065c; complete results are separately recorded in its build results index and cannot inherit the historical SoC execution identity above. The eight current candidates use H743 HSI64/Cache off and U575 MSIS4/TZEN=0 empty/UART baremetal/FreeRTOS reference combinations; this expands no physical-board support. The 72-stage software master plan was not executed as one complete plan invocation. OCI recipe rebuild, CP311 offline installation and physical HIL remain unexecuted. Later documentation commits only record the exact code source.

docs/archive/ retains historical designs, results and old Sphinx tutorials; these confer no current support or acceptance. Current public API documentation is generated only from existing public include trees. Code formatting and backslash Doxygen style retain the root .clang-format, .editorconfig and existing standards.

Behavior changes follow TDD. GoogleTest/GoogleMock enter host test targets only; production firmware remains C11. Commit hooks actually run the complete testing/configure/ci/workflows tool suites and all GoogleTest contracts, rejecting incomplete, filtered or skipped reports. Execution results prove current contracts; actual RED→GREEN history is recorded in PRs and raw logs.