sleep.h File Reference

Reviewed single-CPU shallow sleep contracts. More...

#include "nexus/arch/features.h"

Go to the source code of this file.

Functions
nx_arch_result_t	nx_arch_wait_for_interrupt (void)
	Wait once with configurable exceptions already masked.
nx_arch_result_t	nx_arch_idle_if_unchanged (const uint32_t *sequence, uint32_t expected, bool *slept)
	Atomically recheck a published sequence before WFI.

Detailed Description

Reviewed single-CPU shallow sleep contracts.

Author

Nexus Team

Version

1.0.0

Date

2026-10-11

Copyright

Copyright (c) 2026 Nexus Team

Definition in file sleep.h.

Function Documentation

nx_arch_idle_if_unchanged()

nx_arch_result_t nx_arch_idle_if_unchanged	(	const uint32_t *	sequence,
		uint32_t	expected,
		bool *	slept )

Atomically recheck a published sequence before WFI.

Parameters

[in]	sequence	Naturally aligned, shared 32-bit wake sequence.
[in]	expected	Snapshot before the caller's readiness check.
[out]	slept	True only when WFI was executed.

Returns

OK, INVALID, CONTEXT or UNSUPPORTED.

Note

Privileged Thread mode with all incoming masks clear. Saves PRIMASK, performs acquire observation under that mask, optionally sleeps, and restores the exact mask. Publishers must be same-CPU configurable IRQs or Threads; NMI/HardFault, DMA, SMP and other security-world publishers are excluded. The caller keeps storage alive, owns an enabled IRQ timer for finite deadlines, and retries the authoritative predicate after wake. Native is unsupported.

nx_arch_wait_for_interrupt()

nx_arch_result_t nx_arch_wait_for_interrupt

(

void

)

Wait once with configurable exceptions already masked.

Returns

OK after wake, CONTEXT or UNSUPPORTED without sleeping.

Note

Privileged Thread mode, incoming PRIMASK=1, BASEPRI and FAULTMASK clear. SCR.SLEEPDEEP must be clear. The caller owns the final readiness check and timer/wake source. WFI wakes for a pending enabled interrupt despite PRIMASK; the interrupt runs after the caller restores its saved mask. No register, mask, clock or pending interrupt is changed. Current CPU/security state only; no physical HIL claim.