cache.h File Reference

Explicit whole-line CPU cache maintenance mechanisms. More...

#include "nexus/arch/features.h"
#include <stddef.h>
#include <stdint.h>

Go to the source code of this file.

Functions
nx_arch_result_t	nx_arch_dcache_clean (uintptr_t address, size_t bytes)
	Publish dirty data cache lines to the point of coherency.
nx_arch_result_t	nx_arch_dcache_invalidate (uintptr_t address, size_t bytes)
	Discard complete data cache lines without writing them.
nx_arch_result_t	nx_arch_dcache_clean_invalidate (uintptr_t address, size_t bytes)
	Publish dirty data and discard the complete cache lines.
nx_arch_result_t	nx_arch_instruction_sync (uintptr_t address, size_t bytes)
	Make a complete owned range coherent for CPU instructions.

Detailed Description

Explicit whole-line CPU cache maintenance mechanisms.

Author

Nexus Team

Definition in file cache.h.

Function Documentation

nx_arch_dcache_clean()

nx_arch_result_t nx_arch_dcache_clean	(	uintptr_t	address,
		size_t	bytes )

Publish dirty data cache lines to the point of coherency.

Parameters

[in]	address	First byte of exclusively owned complete lines.
[in]	bytes	Nonzero whole-line length in the CPU address space.

Returns

OK after maintenance and barriers; INVALID for partial lines or an overflowing/non-32-bit range; CONTEXT for an unprivileged caller; UNSUPPORTED for an absent or disabled reviewed cache. Rejection performs no maintenance writes.

Note

Privileged task/configurable-IRQ context in the current security domain only. The caller excludes other CPU, security-world and DMA users of every complete line until return, and keeps cache configuration stable. No hidden IRQ mask, allocation or cache enable occurs. Supported geometry is an explicitly reviewed 32-byte line; range rounding is forbidden. Work is bounded by bytes/32 and is not a DMA drain, device completion or transfer of ownership.

nx_arch_dcache_clean_invalidate()

nx_arch_result_t nx_arch_dcache_clean_invalidate	(	uintptr_t	address,
		size_t	bytes )

Publish dirty data and discard the complete cache lines.

Parameters

[in]	address	First byte of exclusively owned complete lines.
[in]	bytes	Nonzero whole-line length in the CPU address space.

Returns

The same context, range and capability results as clean.

Note

Satisfies clean's exclusion/context contract. Distinct from invalidate: dirty contents are written before discard.

nx_arch_dcache_invalidate()

nx_arch_result_t nx_arch_dcache_invalidate	(	uintptr_t	address,
		size_t	bytes )

Discard complete data cache lines without writing them.

Parameters

[in]	address	First byte of exclusively owned complete lines.
[in]	bytes	Nonzero whole-line length in the CPU address space.

Returns

The same context, range and capability results as clean.

Note

The caller permits all dirty data in these lines to be discarded and satisfies clean's exclusion/context contract. No adjacent line is touched or rounded into the range. For DMA receive, providers coordinate both pre-DMA and post-drain maintenance; this call does not establish idle.

nx_arch_instruction_sync()

nx_arch_result_t nx_arch_instruction_sync	(	uintptr_t	address,
		size_t	bytes )

Make a complete owned range coherent for CPU instructions.

Parameters

[in]	address	First byte of exclusively owned complete lines.
[in]	bytes	Nonzero whole-line length in the CPU address space.

Returns

OK after data clean, instruction invalidate and execution barriers; INVALID/CONTEXT as above; UNSUPPORTED when both reviewed caches are absent or a present cache is disabled.

Note

Satisfies clean's exclusion/context contract. All present caches are checked before any maintenance. With only one reviewed cache, only that cache is maintained. The caller prevents execution from the changing range, including other security-world users. This is not code validation, an MPU policy change or a global cache/branch-predictor flush.