13#define NX_DP83848_TI_ID UINT32_C(0x20005CA0)
14#define NX_DP83848_NS_ID UINT32_C(0x20005C90)
15#define NX_DP83848_10_HALF 1U
16#define NX_DP83848_10_FULL 2U
17#define NX_DP83848_100_HALF 4U
18#define NX_DP83848_100_FULL 8U
nx_result_t nx_dp83848_reset(nx_dp83848_t *phy, nx_time_us_t deadline)
Bounded BMCR soft reset and observed self-clearing acknowledgement.
nx_result_t nx_dp83848_probe(nx_dp83848_t *phy, nx_time_us_t deadline)
Read exact supported identity; mismatch never becomes a default PHY.
nx_result_t nx_dp83848_link(nx_dp83848_t *phy, nx_eth_link_t *link, nx_time_us_t deadline)
Observe latch-low BMSR twice and DP83848 PHYSTS speed/duplex truth.
nx_result_t nx_dp83848_configure(nx_dp83848_t *phy, const nx_dp83848_mode_t *mode, nx_time_us_t deadline)
Start explicit negotiation or fixed mode, never wait for fake link.
Caller-owned untagged Ethernet II frames and receive loans.
Narrow Clause22 station management with absolute deadlines.
nx_result_t
Operation result; success at submission means admission only.
External policy explicitly selects autonegotiation or fixed mode.
Caller-owned PHY state; no board address, reset GPIO or worker default.
const nx_mdio_port_t * mdio
Observed PHY fact, supplied explicitly by the external link owner.
uint64_t nx_time_us_t
Microseconds in one boot/clock domain; no wall-clock semantics.