CPU-local mask, context, ordering and cycle snapshot contract. More...

#include <stdbool.h>
#include <stdint.h>

Data Structures
struct	nx_arch_irq_state_t
	Saved incoming PRIMASK or calling-thread Native nesting. More...
struct	nx_arch_irq_masks_t
	Read-only snapshot of implemented local interrupt masks. More...

Functions
nx_arch_irq_state_t	nx_arch_irq_save (void)
	Save incoming local mask and mask configurable exceptions.
void	nx_arch_irq_restore (nx_arch_irq_state_t previous)
	Restore the incoming mask, preserving nested exclusions.
nx_arch_irq_masks_t	nx_arch_irq_masks (void)
	Snapshot the implemented local interrupt-mask registers.
bool	nx_arch_irq_is_masked (void)
	Test masks that could prevent required completion progress.
uint32_t	nx_arch_exception_number (void)
	Query the exact current CPU exception identity.
bool	nx_arch_is_privileged (void)
	Query privilege in the current CPU execution context.
bool	nx_arch_in_isr (void)
	Query current CPU exception context.
void	nx_arch_dmb (void)
	Order explicit data memory accesses in the CPU domain.
void	nx_arch_dsb (void)
	Complete preceding explicit memory accesses.
void	nx_arch_isb (void)
	Synchronize subsequent CPU instruction execution.
bool	nx_arch_cycle_snapshot (uint32_t *cycles)
	Snapshot an already enabled free-running cycle counter.

Detailed Description

CPU-local mask, context, ordering and cycle snapshot contract.

Author: Nexus Team

Definition in file arch.h.

Function Documentation

◆ nx_arch_cycle_snapshot()

bool nx_arch_cycle_snapshot ( uint32_t * cycles )

Snapshot an already enabled free-running cycle counter.

Parameters

[out] cycles DWT CYCCNT snapshot, unchanged when unavailable.

Returns: True when a maintained CPU counter is enabled; false on Native, an unreviewed/disabled/unavailable DWT, or an unprivileged caller. Does not enable/reset it. Only a reviewed CPU profile may read the optional DWT registers.

Note: Counter frequency follows CPU clock. Use unsigned snapshot subtraction only for intervals shorter than 2^32 cycles; this counter is neither shared monotonic time nor a deadline.

◆ nx_arch_dmb()

void nx_arch_dmb ( void )

Order explicit data memory accesses in the CPU domain.

Note: Cortex-M DMB; Native sequentially consistent thread fence. Does not prove DMA idle or clean noncoherent cache lines.

◆ nx_arch_dsb()

void nx_arch_dsb ( void )

Complete preceding explicit memory accesses.

Note: Cortex-M DSB; Native thread fence is a behavioral model, not a physical bus/DMA completion guarantee.

◆ nx_arch_exception_number()

uint32_t nx_arch_exception_number ( void )

Query the exact current CPU exception identity.

Returns: IPSR exception number, zero for Thread mode or Native.

Note: Bounded read-only task/IRQ query. The identity belongs to the current CPU/security state; it is not a portable SoC IRQ number or evidence that a kernel ISR call is allowed.

◆ nx_arch_in_isr()

bool nx_arch_in_isr ( void )

Query current CPU exception context.

Returns: Cortex-M IPSR is nonzero; Native has no hardware ISR and always returns false. Host signals are unsupported contexts.

◆ nx_arch_irq_is_masked()

bool nx_arch_irq_is_masked ( void )

Test masks that could prevent required completion progress.

Returns: True for PRIMASK, implemented BASEPRI/FAULTMASK, or Native thread nesting. Baseline Cortex-M cores query PRIMASK only.

Note: Bounded privileged task/IRQ query, no state change. ARM unprivileged reads do not establish the actual mask state.

◆ nx_arch_irq_masks()

nx_arch_irq_masks_t nx_arch_irq_masks ( void )

Snapshot the implemented local interrupt-mask registers.

Returns: Current PRIMASK and implemented BASEPRI/FAULTMASK values.

Note: Bounded read-only privileged task/IRQ query. Does not mask interrupts or grant a stable critical section. Values refer to this CPU/security state, not another security world or an SMP peer. Unprivileged reads do not establish mask state.

◆ nx_arch_irq_restore()

void nx_arch_irq_restore ( nx_arch_irq_state_t previous )

Restore the incoming mask, preserving nested exclusions.

Parameters

[in] previous Token from this CPU/thread's latest unmatched save.

Note: Privileged contexts only. Restores PRIMASK only; BASEPRI/FAULTMASK, where present, are not modified.

◆ nx_arch_irq_save()

nx_arch_irq_state_t nx_arch_irq_save ( void )

Save incoming local mask and mask configurable exceptions.

Returns: Token to restore exactly once in reverse nesting order.

Note: Privileged Task/configurable-IRQ short metadata sections only; do not block, allocate, call OS functions, copy large buffers or invoke callbacks. NMI/HardFault remain unmasked. Native uses a recursive host exclusion model, not physical IRQ timing or signal safety. NMI/HardFault must not access shared metadata protected by this mask. ARM unprivileged callers need an explicit privileged gateway owned by their OS.

◆ nx_arch_is_privileged()

bool nx_arch_is_privileged ( void )

Query privilege in the current CPU execution context.

Returns: True in Handler mode or privileged Thread mode. Native always returns true because it has no CPU privilege model.

Note: Bounded read-only task/IRQ query. Handler privilege does not depend on the interrupted Thread's CONTROL.nPRIV. This query does not establish Secure-world ownership.

◆ nx_arch_isb()

void nx_arch_isb ( void )

Synchronize subsequent CPU instruction execution.

Note: Cortex-M ISB; Native thread fence has no pipeline semantics.

Data Structures

Functions