Arch：CPU 机制与能力合同

这些声明来自公共头文件。选择、生命周期、支持的执行模式和物理资源授权范围仍以对应设计及支持记录为准。

arch.h

CPU 本地屏蔽、上下文、内存顺序与周期快照合同。

作者 Nexus Team

函数

nx_arch_irq_state_t nx_arch_irq_save(void)

保存进入时的本地屏蔽状态，并屏蔽可配置异常。

备注

Privileged Task/configurable-IRQ short metadata sections only; do not block, allocate, call OS functions, copy large buffers or invoke callbacks. NMI/HardFault remain unmasked. Native uses a recursive host exclusion model, not physical IRQ timing or signal safety. NMI/HardFault must not access shared metadata protected by this mask. ARM unprivileged callers need an explicit privileged gateway owned by their OS.

返回:

Token to restore exactly once in reverse nesting order.

void nx_arch_irq_restore(nx_arch_irq_state_t previous)

恢复进入时的屏蔽状态，保留嵌套屏蔽区的约束。

备注

Privileged contexts only. Restores PRIMASK only; BASEPRI/FAULTMASK, where present, are not modified.

参数:

  • previous – [in] Token from this CPU/thread’s latest unmatched save.

nx_arch_irq_masks_t nx_arch_irq_masks(void)

读取已实现本地中断屏蔽寄存器的快照。

备注

Bounded read-only privileged task/IRQ query. Does not mask interrupts or grant a stable critical section. Values refer to this CPU/security state, not another security world or an SMP peer. Unprivileged reads do not establish mask state.

返回:

Current PRIMASK and implemented BASEPRI/FAULTMASK values.

bool nx_arch_irq_is_masked(void)

检查可能阻止必要完成推进的屏蔽状态。

备注

Bounded privileged task/IRQ query, no state change. ARM unprivileged reads do not establish the actual mask state.

返回:

True for PRIMASK, implemented BASEPRI/FAULTMASK, or Native thread nesting. Baseline Cortex-M cores query PRIMASK only.

uint32_t nx_arch_exception_number(void)

查询当前 CPU 异常的准确身份。

备注

Bounded read-only task/IRQ query. The identity belongs to the current CPU/security state; it is not a portable SoC IRQ number or evidence that a kernel ISR call is allowed.

返回:

IPSR exception number, zero for Thread mode or Native.

bool nx_arch_is_privileged(void)

查询当前 CPU 执行上下文的特权级。

备注

Bounded read-only task/IRQ query. Handler privilege does not depend on the interrupted Thread’s CONTROL.nPRIV. This query does not establish Secure-world ownership.

返回:

True in Handler mode or privileged Thread mode. Native always returns true because it has no CPU privilege model.

bool nx_arch_in_isr(void)

查询当前 CPU 异常上下文。

返回:

Cortex-M IPSR is nonzero; Native has no hardware ISR and always returns false. Host signals are unsupported contexts.

void nx_arch_dmb(void)

为 CPU 域中的显式数据内存访问建立顺序。

备注

Cortex-M DMB; Native sequentially consistent thread fence. Does not prove DMA idle or clean noncoherent cache lines.

void nx_arch_dsb(void)

完成此前的显式内存访问。

备注

Cortex-M DSB; Native thread fence is a behavioral model, not a physical bus/DMA completion guarantee.

void nx_arch_isb(void)

同步后续 CPU 指令执行。

备注

Cortex-M ISB; Native thread fence has no pipeline semantics.

bool nx_arch_cycle_snapshot(uint32_t *cycles)

读取已启用自由运行周期计数器的快照。

备注

Counter frequency follows CPU clock. Use unsigned snapshot subtraction only for intervals shorter than 2^32 cycles; this counter is neither shared monotonic time nor a deadline.

参数:

  • cycles – [out] DWT CYCCNT snapshot, unchanged when unavailable.

返回:

True when a maintained CPU counter is enabled; false on Native, an unreviewed/disabled/unavailable DWT, or an unprivileged caller. Does not enable/reset it. Only a reviewed CPU profile may read the optional DWT registers.

struct nx_arch_irq_state_t
#include <arch.h>

保存进入时的 PRIMASK 或调用线程的 Native 嵌套状态。

备注

Restore on the same CPU/thread in strict reverse order. This is neither a FreeRTOS BASEPRI token nor an SMP lock.

公共成员

uint32_t value
struct nx_arch_irq_masks_t
#include <arch.h>

已实现本地中断屏蔽状态的只读快照。

备注

Absent BASEPRI/FAULTMASK registers are zero. Native reports PRIMASK as zero or one according to current thread nesting. This snapshot is neither a restore token nor a kernel lock.

公共成员

uint32_t primask
uint32_t basepri
uint32_t faultmask

atomic.h

内联、自然对齐的 32 位发布与读改写端口。

作者 Nexus Team

备注

Storage is a live, naturally aligned uint32_t; all concurrent accesses use these helpers or compatible compiler atomics. Initialize before publishing storage. Load/store use compiler acquire/release operations on all maintained CPUs and never mask interrupts. Other than ARMv6-M, RMW uses compiler lock-free operations; exclusive instruction retries do not establish a fixed cycle bound.

备注

ARMv6-M RMW is CPU-local, bounded saved-PRIMASK exclusion. Only privileged Thread/configurable-IRQ contexts on one CPU may access this domain. NMI/HardFault, unprivileged callers, another core, DMA and another security domain must not access its storage concurrently. It is not an SMP or bus atomic operation. No callback, allocation, blocking call or payload copy occurs while masked.

函数

static inline uint32_t nx_atomic_u32_load_relaxed(const uint32_t *value)

读取一个字，不发布或获取其他数据。

static inline uint32_t nx_atomic_u32_load_acquire(const uint32_t *value)

读取一个字，并通过所观察的发布获取数据。

static inline void nx_atomic_u32_store_relaxed(uint32_t *value, uint32_t desired)

存储一个字，不发布其他数据。

static inline void nx_atomic_u32_store_release(uint32_t *value, uint32_t desired)

通过一次对齐的 release 存储发布此前数据。

static inline bool nx_atomic_u32_compare_exchange_acq_rel(uint32_t *value, uint32_t *expected, uint32_t desired)

强 acq_rel 比较交换，失败时采用 acquire 顺序。

参数:

  • value – [inout] Live naturally aligned word in the caller-owned atomic domain; all concurrent accesses use this contract.

  • expected – [inout] Separate, private caller storage; failure replaces it with the observed value. Success leaves it unchanged.

  • desired – [in] Replacement word stored only when comparison succeeds.

返回:

True only when the original word equals expected and the desired word was stored. No spurious failure is allowed.

static inline uint32_t nx_atomic_u32_fetch_add_acq_rel(uint32_t *value, uint32_t amount)

按模 2^32 以 acq_rel 顺序相加，返回原值。

static inline uint32_t nx_atomic_u32_fetch_add_release(uint32_t *value, uint32_t amount)

按模 2^32 以 release 顺序相加，返回原值。

备注

ARMv6-M conservatively acquires the observed word too.

static inline uint32_t nx_atomic_u32_fetch_sub_acq_rel(uint32_t *value, uint32_t amount)

按模 2^32 以 acq_rel 顺序相减，返回原值。

static inline uint32_t nx_atomic_u32_fetch_sub_release(uint32_t *value, uint32_t amount)

按模 2^32 以 release 顺序相减，返回原值。

备注

ARMv6-M conservatively acquires the observed word too.

cache.h

显式的 CPU 完整缓存行维护机制。

作者 Nexus Team

函数

nx_arch_result_t nx_arch_dcache_clean(uintptr_t address, size_t bytes)

将脏数据缓存行发布到一致性点。

备注

Privileged task/configurable-IRQ context in the current security domain only. The caller excludes other CPU, security-world and DMA users of every complete line until return, and keeps cache configuration stable. No hidden IRQ mask, allocation or cache enable occurs. Supported geometry is an explicitly reviewed 32-byte line; range rounding is forbidden. Work is bounded by bytes/32 and is not a DMA drain, device completion or transfer of ownership.

参数:

  • address – [in] First byte of exclusively owned complete lines.

  • bytes – [in] Nonzero whole-line length in the CPU address space.

返回:

OK after maintenance and barriers; INVALID for partial lines or an overflowing/non-32-bit range; CONTEXT for an unprivileged caller; UNSUPPORTED for an absent or disabled reviewed cache. Rejection performs no maintenance writes.

nx_arch_result_t nx_arch_dcache_invalidate(uintptr_t address, size_t bytes)

丢弃完整数据缓存行，不执行写回。

备注

The caller permits all dirty data in these lines to be discarded and satisfies clean’s exclusion/context contract. No adjacent line is touched or rounded into the range. For DMA receive, providers coordinate both pre-DMA and post-drain maintenance; this call does not establish idle.

参数:

  • address – [in] First byte of exclusively owned complete lines.

  • bytes – [in] Nonzero whole-line length in the CPU address space.

返回:

The same context, range and capability results as clean.

nx_arch_result_t nx_arch_dcache_clean_invalidate(uintptr_t address, size_t bytes)

发布脏数据并丢弃完整缓存行。

备注

Satisfies clean’s exclusion/context contract. Distinct from invalidate: dirty contents are written before discard.

参数:

  • address – [in] First byte of exclusively owned complete lines.

  • bytes – [in] Nonzero whole-line length in the CPU address space.

返回:

The same context, range and capability results as clean.

nx_arch_result_t nx_arch_instruction_sync(uintptr_t address, size_t bytes)

使调用者拥有的完整范围对 CPU 指令保持一致。

备注

Satisfies clean’s exclusion/context contract. All present caches are checked before any maintenance. With only one reviewed cache, only that cache is maintained. The caller prevents execution from the changing range, including other security-world users. This is not code validation, an MPU policy change or a global cache/branch-predictor flush.

参数:

  • address – [in] First byte of exclusively owned complete lines.

  • bytes – [in] Nonzero whole-line length in the CPU address space.

返回:

OK after data clean, instruction invalidate and execution barriers; INVALID/CONTEXT as above; UNSUPPORTED when both reviewed caches are absent or a present cache is disabled.

cache_control.h

显式、自有的 Cortex-M7 冷缓存状态转换。

作者 Nexus Team

宏定义

NX_ARCH_CACHE_DATA

数据缓存责任位，独立于硬件 CCR 位布局。

NX_ARCH_CACHE_INSTRUCTION

指令缓存责任位。

枚举

enum nx_arch_cache_control_result_t

冷转换准入或执行结果。

取值：

enumerator NX_ARCH_CACHE_OK
enumerator NX_ARCH_CACHE_INVALID
enumerator NX_ARCH_CACHE_CONTEXT
enumerator NX_ARCH_CACHE_UNSUPPORTED
enumerator NX_ARCH_CACHE_STATE
enumerator NX_ARCH_CACHE_IO

函数

nx_arch_cache_control_result_t nx_arch_cache_cold_enable(nx_arch_cache_control_t *control, uint32_t mask)

对冷缓存作准入判定，并启用显式选定的缓存。

备注

Reviewed M7 only. Requires privileged Thread, PRIMASK=1, BASEPRI=FAULTMASK=0 and known-clean caches from a trusted reset or prior successful owned clean/disable. CCR bits being zero alone do not prove clean foreign state; never adopt an unknown bootloader state. Caller excludes all other cache users, DMA, NMI and HardFault access to affected memory throughout the transition. It owns memory attributes, execution and coherency policy; enabling a cache does not establish DMA coherence. No IRQ mask changes, allocation or cache adoption occur. Rejected initial admission has no retained responsibility. An IO failure can retain owned_mask/selector_pending; call cold_disable and retain storage until it succeeds.

参数:

  • control – [inout] Exclusively owned, initially empty control object.

  • mask – [in] Nonzero combination of DATA and INSTRUCTION bits.

返回:

OK after verified enable and selector restoration; INVALID for arguments; CONTEXT for unsafe context; UNSUPPORTED for an unreviewed CPU/geometry; STATE for live/foreign caches; IO when a register write is not confirmed by readback.

nx_arch_cache_control_result_t nx_arch_cache_cold_disable(nx_arch_cache_control_t *control)

清理并禁用此控制对象负责的缓存。

备注

Satisfies enable’s exclusion and context contract after every DMA/provider has drained. Rejects enabled caches outside owned_mask. The data clean/disable transition uses a stack-free leaf so no local dirty line can appear between the final clean and CCR update. Its bounded work is four ways times the verified set count, not constant latency. Failed operations remain retryable without adopting a new cache or forgetting the original selector. A zero object is an idempotent no-op on a supported CPU profile.

参数:

  • control – [inout] Same live object passed to cold_enable.

返回:

OK only after cache disable and selector restoration; INVALID, CONTEXT, UNSUPPORTED, STATE or IO retain ownership.

struct nx_arch_cache_control_t
#include <cache_control.h>

调用者拥有的缓存责任与选择器恢复状态。

备注

Zero initialize before first use; do not modify fields or copy a live object. Retain the object until owned_mask and selector_pending are both zero. owned_mask conservatively records cleanup responsibility, not enabled hardware bits.

公共成员

uint32_t owned_mask

保留的数据／指令缓存责任。

uint32_t saved_selector

未完成操作对应的原始 CSSELR。

bool selector_pending

原始选择器的恢复仍未完成。

features.h

已审查的 CPU 机制与无分配结果类型。

作者 Nexus Team

枚举

enum nx_arch_result_t

经过验证的本地 CPU 机制操作结果。

取值：

enumerator NX_ARCH_OK
enumerator NX_ARCH_INVALID
enumerator NX_ARCH_CONTEXT
enumerator NX_ARCH_UNSUPPORTED
enum nx_arch_security_state_t

为此固件镜像编译的安全状态。

取值：

enumerator NX_ARCH_SECURITY_SINGLE
enumerator NX_ARCH_SECURITY_SECURE
enumerator NX_ARCH_SECURITY_NONSECURE

函数

nx_arch_features_t nx_arch_features(void)

查询不可变、编译期确定的 CPU 机制能力。

备注

Read-only Task/IRQ query, no hardware access or discovery.

返回:

Exact reviewed CPU facts; Native reports absent hardware.

struct nx_arch_features_t
#include <features.h>

实际编译的精确 CPU profile 中的已审查机制。

备注

Cache sizes are zero when absent, MPU version is zero, seven or eight. These facts do not prove enabled hardware, memory reachability, cross-domain ownership or HIL status.

公共成员

uint32_t dcache_line_bytes
uint32_t icache_line_bytes
uint8_t mpu_version
bool dwt_cycle_counter
bool sau
nx_arch_security_state_t security_state

mpu.h

分别实现 Armv7-M 与 Armv8-M MPU 编码机制。

作者 Nexus Team

函数

nx_arch_result_t nx_arch_mpu_v7_encode(const nx_arch_mpu_v7_region_t *region, nx_arch_mpu_v7_encoding_t *encoding)

编码准确的 Armv7-M 区域，不访问硬件。

备注

Pure bounded task/IRQ function. Inputs and output must not overlap. This encodes fields, not SoC memory reachability, cache ownership, DMA coherency or product protection policy.

参数:

  • region – [in] Size exponent 5..32, aligned base, AP 0/1/2/3/5/6, TEX 0..7 and raw S/C/B bits. Subregion mask is at most 255 and must be zero for sizes below 256 bytes. A 4 GiB region has base zero. Reserved/implementation-defined TEX/C/B encodings are rejected, never truncated or rounded.

  • encoding – [out] RBAR and enabled RASR; unchanged on failure.

返回:

NX_ARCH_OK or NX_ARCH_INVALID, independent of CPU profile.

nx_arch_result_t nx_arch_mpu_v8_encode(const nx_arch_mpu_v8_region_t *region, nx_arch_mpu_v8_encoding_t *encoding)

编码准确的 Armv8-M 区域，不访问硬件。

备注

Pure bounded task/IRQ function. Inputs and output must not overlap. No address rounding or v7/v8 policy conversion.

参数:

  • region – [in] 32-byte aligned base, inclusive limit ending in 0x1f, base not above limit, AP 0..3, SH 0/2/3 and MAIR index 0..7. The caller owns the corresponding MAIR policy.

  • encoding – [out] RBAR and enabled RLAR; unchanged on failure.

返回:

NX_ARCH_OK or NX_ARCH_INVALID, independent of CPU profile.

nx_arch_result_t nx_arch_mpu_v7_program(uint32_t index, const nx_arch_mpu_v7_region_t *region)

在当前安全世界的 MPU 关闭时，编程一个 Armv7-M 区域。

备注

Privileged Thread only with PRIMASK set and exclusive caller ownership of this MPU. NMI/HardFault/another security world must not modify it. Disables only the selected region, writes its fields, restores incoming RNR and leaves CTRL unchanged. No allocation, OS calls, implicit MPU enable, bulk clear or Secure access to the Non-secure alias.

参数:

  • index – [in] Region number below actual MPU_TYPE.DREGION.

  • region – [in] Fields validated by nx_arch_mpu_v7_encode.

返回:

NX_ARCH_UNSUPPORTED before MMIO for a different/absent compiled MPU; NX_ARCH_INVALID for invalid fields or index; NX_ARCH_CONTEXT for an unprivileged, Handler, unmasked or enabled-MPU caller. Rejection performs no register writes.

nx_arch_result_t nx_arch_mpu_v8_program(uint32_t index, const nx_arch_mpu_v8_region_t *region)

在当前安全世界的 MPU 关闭时，编程一个 Armv8-M 区域。

备注

Privileged masked Thread, disabled MPU and exclusive local ownership required. No MAIR updates or cross-world alias access. Incoming RNR and CTRL are preserved.

参数:

  • index – [in] Region number below actual MPU_TYPE.DREGION.

  • region – [in] Fields validated by nx_arch_mpu_v8_encode.

返回:

Same rejection and ownership rules as v7_program; the compiled MPU must specifically implement Armv8-M.

nx_arch_result_t nx_arch_mpu_v8_attribute_set(uint32_t index, uint32_t attribute)

更新一个 Armv8-M MAIR 字节，不修改相邻字节。

备注

Caller owns valid memory attributes and all regions using this slot. Privileged masked Thread, disabled MPU and exclusive local ownership required. No CTRL or RNR writes, no cache maintenance, and no cross-world register access.

参数:

  • index – [in] Attribute slot 0..7.

  • attribute – [in] Architectural MAIR byte, at most 255. Device encodings are 0x00/0x04/0x08/0x0c; Normal memory uses nonzero outer/inner nibbles other than reserved 0x8.

返回:

NX_ARCH_OK, NX_ARCH_UNSUPPORTED for absent/v7 MPU, NX_ARCH_INVALID for an out-of-range field, or NX_ARCH_CONTEXT under the programming context rules.

struct nx_arch_mpu_v7_region_t
#include <mpu.h>

Armv7-M 区域字段，不包含隐式内存策略。

公共成员

uint32_t base
uint32_t size_log2
uint32_t access
uint32_t tex
uint32_t subregion_disable
bool shareable
bool cacheable
bool bufferable
bool execute_never
struct nx_arch_mpu_v7_encoding_t
#include <mpu.h>

针对调用者选定 RNR 的 Armv7-M 寄存器字，不使用 RBAR.VALID。

公共成员

uint32_t rbar
uint32_t rasr
struct nx_arch_mpu_v8_region_t
#include <mpu.h>

Armv8-M 字段；limit 是准确且包含在范围内的最后一个字节。

公共成员

uint32_t base
uint32_t limit
uint32_t access
uint32_t shareability
uint32_t attribute_index
bool execute_never
struct nx_arch_mpu_v8_encoding_t
#include <mpu.h>

保留独立 MAIR 间接索引的 Armv8-M 寄存器字。

公共成员

uint32_t rbar
uint32_t rlar

nonsecure.h

显式的 NonSecure 非特权地址权限检查。

作者 Nexus Team

枚举

enum nx_arch_nonsecure_access_t

请求的 NonSecure 非特权 CPU 数据访问，不包含执行访问。

取值：

enumerator NX_ARCH_NONSECURE_READ
enumerator NX_ARCH_NONSECURE_READWRITE

函数

nx_arch_result_t nx_arch_nonsecure_check(const void *address, size_t bytes, nx_arch_nonsecure_access_t access)

检查当前 NonSecure 非特权上下文对完整范围的访问权限。

备注

Allocation-free permission observation only. Hardware CMSE checks both security attribution and NonSecure MPU rights as an unprivileged caller. Adjacent permitted regions may be conservatively rejected. No memory is copied, pinned or borrowed. Success neither authenticates a gateway caller nor proves RAM, DMA reachability, lifetime or fault safety. The integrating owner must exclude MMIO through its SoC RAM policy and prevent attribution/mapping changes through the subsequent access. Interrupts, another world, DMA and faults are not excluded here; no masks or hardware policy are changed. A gateway must separately snapshot its input and validate output before any irreversible operation.

参数:

  • address – [in] Non-null start; never dereferenced by this API.

  • bytes – [in] Positive length with a representable inclusive end.

  • access – [in] Exact READ or READWRITE access, never a bit mask.

返回:

OK for complete current access; INVALID for malformed or denied spans; CONTEXT outside privileged Secure Thread; UNSUPPORTED in Native, single-state or NonSecure images.

security.h

本地安全状态与显式 SAU 区域机制。

作者 Nexus Team

函数

nx_arch_security_state_t nx_arch_security_state(void)

查询此镜像的编译期安全状态。

备注

Bounded read-only Task/IRQ query, no hardware access. This does not grant access to another world’s memory or devices.

返回:

Single-domain, Secure or NonSecure reviewed image state.

nx_arch_result_t nx_arch_sau_encode(const nx_arch_sau_region_t *region, nx_arch_sau_words_t *words)

编码显式 SAU 区域，不访问硬件。

备注

Pure Task/IRQ operation. Encoding marks the requested region enabled but does not enable SAU hardware. External policy owns overlap, IDAU restrictions and NSC veneers.

参数:

  • region – [in] Base aligned to 32 bytes; inclusive limit ending at a complete 32-byte boundary. Base must not exceed limit.

  • words – [out] Encoded region, unchanged on failure.

返回:

OK or INVALID for null arguments or invalid boundaries.

nx_arch_result_t nx_arch_sau_write(uint32_t index, const nx_arch_sau_region_t *region)

SAU 关闭时，编程一个自有 SAU 区域。

备注

Secure privileged Thread with incoming PRIMASK set only. Caller excludes all other region/selector users and keeps NMI/HardFault outside this metadata. Requires reviewed SAU region support. Does not modify CTRL, ALLNS, another region, another security world’s registers or enable the SAU. Current RNR is restored; DSB/ISB complete region writes. Policy, secure gateways and IDAU configuration stay external.

参数:

  • index – [in] Region index below the actual hardware TYPE count.

  • region – [in] Explicit reviewed region and NSC permission.

返回:

OK, INVALID, CONTEXT or UNSUPPORTED without retained state.

nx_arch_result_t nx_arch_sau_clear(uint32_t index)

SAU 关闭时，禁用一个自有 SAU 区域。

备注

Same context and ownership contract as nx_arch_sau_write. Preserves CTRL, ALLNS, other regions and incoming RNR.

参数:

  • index – [in] Region index below the actual hardware TYPE count.

返回:

OK, INVALID, CONTEXT or UNSUPPORTED without other writes.

struct nx_arch_sau_region_t
#include <security.h>

由 Secure 调用者拥有、准确按 32 字节对齐的 SAU 区域。

公共成员

uint32_t base
uint32_t limit
bool nonsecure_callable
struct nx_arch_sau_words_t
#include <security.h>

经过验证的 SAU 寄存器字；编码不会改变硬件。

公共成员

uint32_t rbar
uint32_t rlar

sleep.h

已审查的单 CPU 浅睡眠合同。

作者 Nexus Team 版本 1.0.0 日期 2026-10-11 版权 Copyright (c) 2026 Nexus Team

函数

nx_arch_result_t nx_arch_wait_for_interrupt(void)

在可配置异常已被屏蔽的条件下等待一次。

备注

Privileged Thread mode, incoming PRIMASK=1, BASEPRI and FAULTMASK clear. SCR.SLEEPDEEP must be clear. The caller owns the final readiness check and timer/wake source. WFI wakes for a pending enabled interrupt despite PRIMASK; the interrupt runs after the caller restores its saved mask. No register, mask, clock or pending interrupt is changed. Current CPU/security state only; no physical HIL claim.

返回:

OK after wake, CONTEXT or UNSUPPORTED without sleeping.

nx_arch_result_t nx_arch_idle_if_unchanged(const uint32_t *sequence, uint32_t expected, bool *slept)

执行 WFI 前，以原子方式重新检查已发布序列。

备注

Privileged Thread mode with all incoming masks clear. Saves PRIMASK, performs acquire observation under that mask, optionally sleeps, and restores the exact mask. Publishers must be same-CPU configurable IRQs or Threads; NMI/HardFault, DMA, SMP and other security-world publishers are excluded. The caller keeps storage alive, owns an enabled IRQ timer for finite deadlines, and retries the authoritative predicate after wake. Native is unsupported.

参数:

  • sequence – [in] Naturally aligned, shared 32-bit wake sequence.

  • expected – [in] Snapshot before the caller’s readiness check.

  • slept – [out] True only when WFI was executed.

返回:

OK, INVALID, CONTEXT or UNSUPPORTED.