HIL and physical-board status

No executable MCU boards, debug probes or serial ports are currently connected. Physical status for F407ZG Qiming, F407VE Sky Star, F470ZG Liangshan, and the G474/H743/U575 source-reference slices is not_executed. Prepared tooling, a successfully generated plan or a passing host validator is not an experiment actually performed on an MCU.

Pending execution scope

Existing entry

Real evidence still needed

Three initial boards and chip-reference configurations

Support records, general HIL preparation

PCB, probe, supply, oscillator, wiring and station admission

Actual UART/SPI/ADC/Flash and other modes

Qualification contract

Raw traces for IRQ, DMA, wire completion, cancellation drain, overload and power loss

OS49–OS55

Original OS records, per-task OS ledger

IRQ-to-task, register retention, stack peaks, Tick, full-load shutdown, sleep and fault response

H743 Cache/DMA and U575 security domains

SoC extension records

Exact supply/option bytes and actual hardware execution, isolation and failure observations

cycles、latency、power、WCET

Later iterations

Actual measurements with the same candidate, instruments, load and explicit budgets

OS plans remain prepared_unbound; physical status remains not_executed. Real execution first requires station admission and an accurate workload, instrument, raw trace, time and target identity. Do not enter passed on an unbound plan as a substitute for acquisition.

First physical-board acceptance sequence

  1. Check the exact PCB, option bytes, electrical conditions, safe initial levels and clock; do not guess wiring.

  2. Bind actual probes, serial ports and required waveform/power-cut instruments to the station.

  3. Fix the source, resolved configuration, tools and candidate ELF; use actual budgets.

  4. Acquire raw observations and exercise failure paths for the selected mode, retaining every failure and retry.

  5. Assess qualification for that exact tuple. Controllers, modes or boards not executed remain unexecuted.

Tool source entry points are in the implementation map. Physical scope advances only after execution at a real station, never because of documentation publication, software CI or on-chip capability.