atomic.h File Reference

Inline naturally aligned 32-bit publication and RMW ports. More...

#include <limits.h>
#include <stdbool.h>
#include <stdint.h>

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Detailed Description

Inline naturally aligned 32-bit publication and RMW ports.

Author

Nexus Team

Note

Storage is a live, naturally aligned uint32_t; all concurrent accesses use these helpers or compatible compiler atomics. Initialize before publishing storage. Load/store use compiler acquire/release operations on all maintained CPUs and never mask interrupts. Other than ARMv6-M, RMW uses compiler lock-free operations; exclusive instruction retries do not establish a fixed cycle bound.

ARMv6-M RMW is CPU-local, bounded saved-PRIMASK exclusion. Only privileged Thread/configurable-IRQ contexts on one CPU may access this domain. NMI/HardFault, unprivileged callers, another core, DMA and another security domain must not access its storage concurrently. It is not an SMP or bus atomic operation. No callback, allocation, blocking call or payload copy occurs while masked.

Definition in file atomic.h.